The present invention relates generally to a semiconductor device, and, more particularly, to a test method and test system for a plurality of memory circuits in a semiconductor device.
Recently, some semiconductor devices (LSIs) have a processing circuit (CPU) and a plurality of memory circuits, which are formed on a single semiconductor substrate. LSIs are tested before shipment. Increasing the scale of LSIs lengthens the time for the operational test, resulting in an increase in production cost. To avoid such increase in production cost, therefore, the testing time should be shortened.
There are three conventional methods known in the industry for conducting an operational test on each of a plurality of memory circuits.
(First method) A testing apparatus selects and tests individual memory circuits one after another.
(Second method) The individual memory circuits are accessed via a plurality of external terminals, and a testing apparatus conducts a test by directly accessing a plurality of memory circuits via the plurality of external terminals and simultaneously performing a write/read operation on all of the memory circuits.
(Third method) A test is conducted by comparing read data from all of the memory circuits with one another in an LSI, outputting signals indicating whether read data from all of the memory circuits match with one another from output terminals, and comparing the output signals with one another.
These conventional methods have the following drawbacks:
In the first method, since the individual memory circuits are tested serially one after another, the testing time becomes longer as the number and capacity of memories in a single LSI become large. Thus, as the scale of LSIs increases, unavoidably, so does the production cost.
Because the second method performs an operational test on a plurality of memory circuits simultaneously, the testing time is shortened. The tradeoff is that the number of external terminals of the LSI increases. To prevent the number of external terminals from increasing, the external terminals may selectively be operated between a test mode and a normal operation mode. In this case, however, the number of output signals in the test mode increases, thus complicating the switching the functions of the terminals. Furthermore, in cases where the number of external terminals of an LSI cannot be increased, the number of memory circuits that can simultaneously be subjected to a test is also limited.
The third method uses fewer output terminals than the second method. According to the third method, however, in cases where all of the output signals of a plurality of memory circuits have the same value but in error, the error cannot be detected. The fewer the memory circuits that simultaneously output read data is (e.g., when two memory circuits simultaneously output read data), the higher the ratio of occurrence of such errors becomes.
What is more, since the first and second methods access each memory circuit in an LSI via an associated external terminal, a testing apparatus having a relatively slow operational speed may not be able to shorten the testing time so much. Similarly, the third method outputs a test result according to the operational speed of an LSI. In cases where the operational speed of the testing apparatus is slower than that of the LSI, the testing apparatus cannot receive all of the test results. In other words, a test cannot be conducted at the operational speed of the LSI.